1. Field of the Invention
This invention relates to integrated circuit (IC) manufacture technology, and more particularly, to a wafer level IC structure and a method of manufacturing this wafer level IC structure, which can help increase the yield of the IC manufacture.
2. Description of Related Art
In the semiconductor industry, IC design and fabrication is directed to high integration, high speed, high throughput, and low cost. In practice, however, 100% yield is nearly impossible, particularly for high-integration wafer level IC devices. The yield of IC manufacture is customarily defined in terms of density of defects, which can be minimized through good circuit design and the use of good repair technology. As an IC device is increased in layout size, it would also increase the probability of an increased number of defects; and therefore, the manufacture of wafer level IC devices is typically lower in yield than the manufacture of chip-sized IC devices. For wafer level memory devices, the nature yield is typically below 50%. Especially for wafer level DRAM devices, the nature yield is much lower.
A wafer level integration circuit allows a number of chips which are of different kinds to be mounted in a single wafer, which can provide an increased level of functionality and a reduced signal transmission path for higher performance. One drawback to the wafer level integration circuit, however, is that it is highly complex in structure, resulting in low yield and high manufacture cost, and is therefore only used in some special high-level products such as supercomputers.
One solution to increase yield in the manufacture of chip-sized memory devices is to provide a redundant circuit in each memory device so that each inoperative memory cell, if any, can be replaced by a backup one in the redundant circuit. One drawback to this solution, however, is that it is only suitable for use on chip-sized IC devices and unsuitable for use on wafer level integration circuit since it would be difficult to integrate a redundant circuit in a wafer level integration circuit. Meanwhile, this solution would increase the die size so that increases the manufacturing cost. Another solution is to use the so-called discretionary wiring method, by which only operative components, excluding inoperative ones, that are checked out during testing are wired. One drawback to this solution, however, is that various photomasks, and not a single one, might be required to perform the wiring for different IC devices since different IC devices may not have inoperative components at the same locations. This drawback makes the discretionary wiring method very costly to implement.
The U.S. Pat. No. 4,703,436 discloses a wafer level IC structure for SRAM (static random-access memory) which includes a plurality of discrete memory chips and is characterized in the use of a multi-layer interconnect structure for interconnecting these discrete memory chips. Moreover, this patented structure utilizes a plurality of fuses for selective disconnection of inoperative components from active use. One drawback to this patented structure, however, is that the provision of these fuses and the use of additional test pads during testing would undesirably increase the overall layout area of the IC device and the manufacturing cost, making the resulted IC device quite bulky. Moreover, this patented structure is only suitable for SRAM fabrication but unsuitable for DRAM fabrication.
The U.S. Pat. No. 5,072,424 proposes a wafer level IC structure for DRAM, which is characterized in the use of a serial looping chain structure to interconnect the memory cells and allow these memory cells to be tested through software means. Inoperative memory cells, if any, can be replaced by logic control means through EEPROM. One drawback to this patented structure, however, is that the required refreshing process would make the operation very complex. Moreover, the use of software means for access operation would considerably slow down the access speed to the DRAM.
The U.S. Pat. No. 5,576,554 discloses a wafer level IC structure which includes a plurality of IC modules and is characterized in the use of the blank areas among the IC modules to form a chessboard-like interconnect structure serving as a bi-directional bus. Further, this patented structure is formed with a plurality of fuses at the intersections of the chessboard-like interconnect structure for selective disconnection of inoperative components, if any, from active use. This patented structure, however, is still unsatisfactory to use.